The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Sep. 15, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Yi Tang, Hefei, CN;

Jianfeng Xiao, Hefei, CN;

Xiaojie Li, Hefei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H10B 51/30 (2023.01); H10B 53/30 (2023.01);
U.S. Cl.
CPC ...
H10B 12/30 (2023.02); H10B 12/48 (2023.02); H10B 12/482 (2023.02); H10B 12/485 (2023.02); H10B 51/30 (2023.02); H10B 53/30 (2023.02);
Abstract

Embodiments relate to the field of semiconductors, and provide a semiconductor structure, including a substrate and connection lines. Structural cells arranged in an array are provided on the substrate, and include transistor groups arranged in a first direction, and the transistor groups include multi-layer transistors extending in a second direction. The first direction is perpendicular to the second direction, and both are parallel to a surface of the substrate. The structural cells further include bit lines extending in a third direction, the bit lines are electrically connected to the multi-layer transistors in the same transistor group, where the third direction is perpendicular to the surface of the substrate. The connection lines are connected to the bit lines in the structural cells in one-to-one correspondence, and one bit line in the structural cells arranged in the array is connected to the same connection line.


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