The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Jun. 17, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Choongbin Yim, Seoul, KR;

Jinwoo Park, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/563 (2013.01); H01L 23/3121 (2013.01); H01L 23/49811 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/2929 (2013.01); H01L 2224/29386 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/92125 (2013.01);
Abstract

A semiconductor package includes: a package substrate; a semiconductor chip mounted above the package substrate; a chip connection terminal interposed between the semiconductor chip and the package substrate; an adhesive layer disposed on the package substrate and that covers a side and a top surface of the semiconductor chip and surrounds the chip connection terminal between the semiconductor chip and the package substrate; a molding layer disposed on the package substrate and that surrounds the adhesive layer; an interposer mounted on the adhesive layer and the molding layer, where the interposer includes an interposer substrate; and a conductive pillar disposed on the package substrate, where the conductive pillar surrounds the side of the semiconductor substrate, penetrates the molding layer in a vertical direction and connects the package substrate to the interposer substrate.


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