The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Oct. 15, 2021
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Yun-Yuan Wang, Kaohsiung, TW;

Ming-Liang Wei, Kaohsiung, TW;

Ming-Hsiu Lee, Hsinchu, TW;

Cheng-Hsien Lu, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/11 (2006.01); G06G 7/32 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G06F 17/11 (2013.01); G06G 7/32 (2013.01); G11C 16/26 (2013.01);
Abstract

A memory device and a computing method thereof are provided in the present disclosure. The computing method includes the following steps. A plurality of input-values of a model computation are respectively received through a plurality of first-word-lines of a memory array. Inverted logic values of the input-values are respectively received through a plurality of second-word-lines. The input-values are respectively received through a plurality of first-bit-lines. The inverted logic values are respectively received through a plurality of second-bit-lines. Logic XNOR operation is performed according to each of the input-values and each of the inverted values to obtain a first computation result, and multiplied with one of self-coefficients or one of mutual coefficients of the model computation to obtain a plurality of output-values. The output-values are outputted through a plurality of common-source-lines.


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