The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Mar. 18, 2024
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Weihuang Wang, Santa Clara, CA (US);

Alessandro Fulli, Boxborough, MA (US);

Alexandru Seibulescu, Santa Clara, CA (US);

Kecheng Qian, Santa Clara, CA (US);

Kit Chiu Chu, Freemont, CA (US);

Mahesh Machineni, Santa Clara, CA (US);

Michael Brian Galles, Los Altos, CA (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01);
Abstract

Embodiments herein describe selectively bypassing a networking pipeline in a DPU. For example, instead of a packet being processed by both the networking pipeline and a DMA pipeline in the DPU, the packet is only processed by the DMA pipeline. This can reduce latency for packets that do not have network-heavy tasks associated with them, such Remote Direct Memory Access (RDMA) over Converged Ethernet (RoCE) packets. In addition, the DPU can perform load balancing between different instances of the pipelines in the DPU.


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