Back-end-of-line semiconductor device structure providing a not-gate logic function and methods of forming the same

Abstract

A semiconductor device structure providing a NOT gate logic function includes a layer stack including a pair of semiconductor layers having opposite conductivity-types, and a dielectric isolation layer disposed therebetween. First and second electrodes are located on a first side of the layer stack, where the first electrode contacts a first side surface of a first semiconductor layer and a second electrode contacts a first side surface a second semiconductor layer. A third electrode located on a second side of the layer stack contacts a second side surface of the first semiconductor layer and a second side surface of the second semiconductor layer. A gate dielectric layer is located over two side surfaces of the layer stack. A pair of gate electrodes located on either side of the layer stack contacts the gate dielectric layer. The semiconductor device structure may be fabricated using a BEOL process using metal-oxide semiconductor materials.