The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Aug. 05, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jia-Chuan You, Hsinchu, TW;

Kuan-Ting Pan, Hsinchu, TW;

Shi Ning Ju, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu, TW;

Chih-Hao Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/258 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/017 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

A semiconductor device includes an active area extending in a first direction over a substrate, the active area including at least one conductive path extending from a source region, through a channel region, to a drain region; and a gate dielectric on a surface of the at least one conductive path in the channel region. The semiconductor device also includes an isolating fin at a first side of the active area, the isolating fin having a first fin region having a first fin width adjacent to the source region, a second fin region having a second fin width adjacent to the channel region, and a third fin region having the first fin width adjacent to the drain region; and a gate electrode against the gate dielectric in the channel region.


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