The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Mar. 13, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Ming-Hua Tsai, Tainan, TW;

Chin-Chia Kuo, Tainan, TW;

Wei-Hsuan Chang, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/60 (2025.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 30/603 (2025.01); H10D 30/0227 (2025.01);
Abstract

A transistor with an embedded insulating structure set includes a substrate. A gate is disposed on the substrate. A first lightly doped region is disposed at one side of the gate. A second lightly doped region is disposed at another side of the gate. The first lightly doped region and the second lightly doped region have the same conductive type. The first lightly doped region is symmetrical to the second lightly doped region. A first source/drain doped region is disposed within the first lightly doped region. A second source/drain doped region is disposed within the second lightly doped region. A first insulating structure set is disposed within the first lightly doped region and the first source/drain doped region. The first insulating structure set includes an insulating block embedded within the substrate. A sidewall of the insulating block contacts the gate dielectric layer.


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