The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Jun. 06, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Da-Jun Lin, Kaohsiung, TW;

Chih-Wei Chang, Tainan, TW;

Fu-Yu Tsai, Tainan, TW;

Bin-Siang Tsai, Changhua County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H01L 21/265 (2006.01); H01L 23/31 (2006.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01); H10D 64/62 (2025.01);
U.S. Cl.
CPC ...
H10D 30/015 (2025.01); H01L 21/26546 (2013.01); H01L 23/3171 (2013.01); H10D 30/475 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 62/8503 (2025.01); H10D 64/01 (2025.01); H10D 64/411 (2025.01); H10D 64/62 (2025.01);
Abstract

A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A passivation layer is formed on the III-V compound barrier layer. A silicon layer is formed on the passivation layer, the III-V compound barrier layer, and the III-V compound semiconductor layer. A silicon implantation process is performed to the III-V compound semiconductor layer for forming a source doped region and a drain doped region in the III-V compound semiconductor layer under the silicon layer. A source electrode and a drain electrode are formed on the silicon layer. A source silicide layer is formed between the source electrode and the source doped region, and a drain silicide layer is formed between the drain electrode and the drain doped region. The source silicide layer and the drain silicide layer are partly formed on the passivation layer.


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