The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2025
Filed:
Jul. 01, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/285 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76865 (2013.01); H01L 21/76885 (2013.01); H01L 23/5226 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 21/28568 (2013.01);
Abstract
The present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. One or more lower interconnects are disposed within a lower inter-level dielectric (ILD) structure over the substrate. A plasma induced damage (PID) mitigation layer is disposed over the lower ILD structure. The PID mitigation layer has a porous structure including a metal. A first upper interconnect is laterally surrounded by an upper ILD structure over the PID mitigation layer. The first upper interconnect extends from over the PID mitigation layer to the one or more lower interconnects.