The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Apr. 20, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yasir Mohsin Husain, Folsom, CA (US);

Everardo Flores, Iii, Penryn, CA (US);

Neeladri Sain, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4094 (2006.01); G11C 11/404 (2006.01); G11C 11/408 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4085 (2013.01); G11C 11/4045 (2013.01); G11C 11/4094 (2013.01); H03K 19/20 (2013.01);
Abstract

A memory device comprising a plurality of first global access lines, second global access lines, first local access lines, and second local access lines; and a plurality of memory cells, wherein a memory cell is coupled to one of the first local access lines and one of the second local access lines. The memory device further comprises a plurality of signal lines to communicate local access line select signals to control a plurality of select devices, wherein a select device selectively couples one of the first global access lines to one of the first local access lines; and a NOR gate to accept the plurality of local access line select signals as inputs and generate a plurality of local access line deselect signals to control a plurality of deselect devices, wherein a deselect device selectively couples one of the first local access lines to a deselect voltage.


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