Page request interface (pri) handler operational support in relation to caching host memory address translation data in a memory sub-system

Abstract

A processing device includes host interface circuitry to interact with a host system and an address translation circuit to handle address translation requests to the host system from host interface circuits. The address translation circuit includes a cache to store address translations associated with the address translation requests for future access by host interface circuits. A page request interface (PRI) handler tracks translation miss messages received from the host interface circuits, each translation miss message including a virtual address of a miss at the cache. The PRI handler removes duplicate translation miss messages having an identical virtual address and creates page miss requests from non-duplicate translation miss messages that are categorized into page request groups, each page request group corresponding to a host interface circuit of the host interface circuits. The PRI handler queues the page request groups to be sent to a translation agent of the host system.