The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Dec. 14, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Anant Vithal Nori, Bangalore, IN;

Prathmesh Kallurkar, Bangalore, IN;

Niranjan Kumar Soundararajan, Bengalaru, IN;

Sreenivas Subramoney, Bangalore, IN;

Lihu Rappoport, Haifa, IL;

Hanna Alam, Jish, IL;

Adrian Moga, Portland, OR (US);

Ronak Singhal, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/084 (2016.01);
U.S. Cl.
CPC ...
G06F 12/084 (2013.01); G06F 2212/62 (2013.01);
Abstract

Methods and apparatus relating to de-prioritizing speculative code lines in on-chip caches are described. In an embodiment, logic circuitry determines whether a storage structure includes a reference to a code miss request prior to transmission of the code miss request to a shared cache. The logic circuitry causes de-prioritization of a code line, corresponding to the code miss request, in the shared cache in response to an absence of the reference in the storage structure. Other embodiments are also disclosed and claimed.


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