The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 16, 2025

Filed:

Apr. 08, 2023
Applicant:

Sambanova Systems, Inc., Palo Alto, CA (US);

Inventors:

Darshan Gandhi, Palo Alto, CA (US);

Manish K. Shah, Austin, TX (US);

Raghu Prabhakar, San Jose, CA (US);

Gregory Frederick Grohoski, Bee Cave, TX (US);

Youngmoon Choi, Milpitas, CA (US);

Jinuk Shin, San Jose, CA (US);

Assignee:

SambaNova Systems, Inc., Palo Alto, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3206 (2019.01); G06F 1/08 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3206 (2013.01); G06F 1/08 (2013.01);
Abstract

An integrated circuit (IC) includes an array of statically reconfigurable compute units for separation into mutually exclusive groups. Each group includes statically reconfigurable number of compute units. Each compute unit includes a register statically reconfigurable with a group identifier that identifies which group the compute unit belongs to, a counter statically reconfigurable to synchronously increment with the counters of all the other compute units such that all the counters have the same value each clock cycle, and control circuitry that prevents the compute unit from starting to process data until the counter value matches the identifier. According to operation of the register, the counter, and the control circuitry, no more than the statically reconfigurable number of the compute units are allowed to start processing data concurrently to mitigate supply voltage droop caused by a time rate of change of current drawn by the IC through inductive loads of the IC.


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