The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2025
Filed:
Jul. 05, 2024
Intel Corporation, Santa Clara, CA (US);
Vasudevan Srinivasan, Portland, OR (US);
Krishnakanth V. Sistla, Portland, OR (US);
Corey D. Gough, Hillsboro, OR (US);
Ian M. Steiner, Portland, OR (US);
Nikhil Gupta, Portland, OR (US);
Vivek Garg, Folsom, CA (US);
Ankush Varma, Portland, OR (US);
Sujal A. Vora, San Jose, CA (US);
David P. Lerner, Santa Clara, CA (US);
Joseph M. Sullivan, Santa Clara, CA (US);
Nagasubramanian Gurumoorthy, Portland, OR (US);
William J. Bowhill, Framingham, MA (US);
Venkatesh Ramamurthy, Portland, OR (US);
Chris Macnamara, Limerick, IE;
John J. Browne, Limerick, IE;
Ripan Das, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.