The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

Jul. 10, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chung-Ting Ko, Kaohsiung, TW;

Wen-Ju Chen, New Taipei, TW;

Tai-Chun Huang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/00 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/017 (2025.01); H01L 21/0259 (2013.01); H01L 21/30604 (2013.01); H01L 21/3081 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/021 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0167 (2025.01); H10D 84/0172 (2025.01); H10D 84/0184 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract

A method for forming a semiconductor structure is provided. The method includes forming a first active region and a second active region, etching the first active region and the second active region to form a first recess and a second recess, respectively, forming the first dielectric layer over the first active region and the second active region, forming a first fill layer over the first dielectric layer to overfill the first recess and the second recess, forming a first dielectric mask over the first fill layer, etching first portions of the first dielectric mask and the first fill layer over the first active region, removing a first portion of the first dielectric layer over the first active region, and forming a first source/drain feature on the first active region.


Find Patent Forward Citations

Loading…