The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2025
Filed:
Aug. 29, 2023
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Jitendra Kumar Yadav, Bengaluru, IN;
Sachin Ramesh Gugwad, Karnataka, IN;
Hari Anand Ravi, Karnataka, IN;
Hajee Mohammed Shuaeb Fazeel, Bengaluru, IN;
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/06 (2006.01); H03K 19/003 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
H03K 5/06 (2013.01); H03K 19/00384 (2013.01); H03K 19/1737 (2013.01);
Abstract
A high-speed clocking circuit may include a single path digitally controlled coarse delay line including multiple stages. Each of the multiple stages may include a plurality of inverters and a logic gate electrically connected in series that are configured to enable a forward path of the single path digitally controlled coarse delay line prior to disabling a return path of the single path digitally controlled coarse delay line to minimize glitching.