The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

Nov. 15, 2019
Applicant:

San-ei Kagaku Co., Ltd., Tokyo, JP;

Inventor:

Hiroyuki Kurihara, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 24/19 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H01L 24/24 (2013.01); H01L 2224/2402 (2013.01); H01L 2224/24225 (2013.01); H01L 2224/245 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/15747 (2013.01);
Abstract

A via wiring formation substrate for mounting at least one semiconductor chip, the substrate including a support substrate, a releasable adhesive layer provided on the support substrate, a first insulating layer provided on the releasable adhesive layer, and a second insulating layer laminated on the first insulating layer, wherein the first insulating layer and the second insulating layer are provided with a via wiring formation via, the via wiring formation via enabling formation of via wirings which respectively correspond to a plurality of connection terminals of the semiconductor chip and which respectively connect the plurality of connection terminals, such that the via wiring formation via penetrates only through the first insulating layer and the second insulating layer without misalignment.


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