The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

May. 13, 2024
Applicant:

Parabellum Strategic Opportunities Fund Llc, Wilmington, DE (US);

Inventors:

Chia-Hao Chang, Hsinchu, TW;

Jia-Chuan You, Taoyuan, TW;

Yu-Ming Lin, Hsinchu, TW;

Chih-Hao Wang, Hsinchu, TW;

Wai-Yi Lien, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/535 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10D 30/69 (2025.01); H10D 62/00 (2025.01); H10D 64/01 (2025.01); H10D 62/13 (2025.01); H10D 62/822 (2025.01);
U.S. Cl.
CPC ...
H01L 21/76895 (2013.01); H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 23/528 (2013.01); H01L 23/535 (2013.01); H10D 30/797 (2025.01); H10D 62/021 (2025.01); H10D 64/017 (2025.01); H10D 62/151 (2025.01); H10D 62/822 (2025.01);
Abstract

A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The dielectric liner surrounds the conductive structure and is over the top surface of the source/drain contact.


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