The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

May. 04, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Hsiu Hsieh, Hsinchu, TW;

Hsiao-Wen Chung, Taipei, TW;

Shan-Yu Huang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2025.01); G06F 30/392 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
H01L 21/28 (2013.01); G06F 30/392 (2020.01); G06F 2119/18 (2020.01);
Abstract

A method for fabricating a semiconductor device is provided. The method includes generating a redistribution layer (RDL) layout, wherein the RDL layout comprises a plurality of redistribution lines; determining a first dummy region in the RDL layout according to the redistribution lines; disposing a plurality of first dummy redistribution lines in the first dummy region; performing a first modification process to enlarge at least one of the first dummy redistribution lines; determining the enlarged one of the first dummy redistribution lines as a second dummy region in the RDL layout when an area of the enlarged one of the first dummy redistribution lines is greater than a threshold value; disposing a plurality of second dummy redistribution lines in the second dummy region; and patterning a metal layer according to the RDL layout after disposing the second dummy redistribution lines in the second dummy region.


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