The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 09, 2025

Filed:

Nov. 17, 2023
Applicant:

Rambus Inc., San Jose, CA (US);

Inventors:

Frederick A. Ware, Los Altos Hills, CA (US);

Kenneth L. Wright, Sunnyvale, CA (US);

John Eric Linstadt, Palo Alto, CA (US);

Craig Hampel, Los Altos, CA (US);

Assignee:

Rambus Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06F 12/0868 (2016.01); G06F 12/0888 (2016.01); G06F 12/0895 (2016.01); G06F 13/28 (2006.01); G11C 7/10 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1678 (2013.01); G06F 3/0604 (2013.01); G06F 3/0613 (2013.01); G06F 3/0619 (2013.01); G06F 3/0634 (2013.01); G06F 3/0656 (2013.01); G06F 3/0673 (2013.01); G06F 11/1004 (2013.01); G06F 11/1068 (2013.01); G06F 12/0868 (2013.01); G06F 12/0888 (2013.01); G06F 12/0895 (2013.01); G06F 13/28 (2013.01); G11C 7/10 (2013.01); G11C 29/52 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/403 (2013.01);
Abstract

A memory controller includes an interface to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space. At least a portion of the DRAM storage space is configured as a cache for the SCM storage space. The interface to receive an incoming tag address for a read operation. Tag comparison circuitry performs a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache. The data in the addressed DRAM cache space is selectively provided directly to the memory controller as first read data based on the results of the comparison.


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