The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Jul. 11, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chun-Hsu Yen, Hsinchu, TW;

Yu-Chuan Hsu, Hsinchu, TW;

Chen-Hui Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H10N 70/8413 (2023.02); H10B 63/30 (2023.02); H10N 70/011 (2023.02); H10N 70/063 (2023.02); H10N 70/231 (2023.02); H10N 70/8265 (2023.02); H10N 70/8825 (2023.02); H10N 70/8828 (2023.02); H10N 70/884 (2023.02); G11C 13/0004 (2013.01); H10B 63/84 (2023.02); H10N 70/041 (2023.02); H10N 70/066 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/881 (2023.02); H10N 70/8833 (2023.02);
Abstract

A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.


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