The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Jul. 21, 2022
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chien-Hung Chen, Taipei, TW;

Ruei-Yau Chen, Pingtung County, TW;

Wei-Jen Wang, Tainan, TW;

Kun-Yuan Wu, Kaohsiung, TW;

Chien-Fu Chen, Miaoli County, TW;

Chen-Hsien Hsu, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/90 (2025.01); G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
H10D 84/907 (2025.01); G06F 30/392 (2020.01); H10D 84/981 (2025.01);
Abstract

A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.


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