The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Aug. 23, 2024
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Richard Taylor, Iii, Campbell, CA (US);

Andreas Knorr, Saratoga Springs, NY (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 86/00 (2025.01); H10D 62/13 (2025.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H10D 62/151 (2025.01); H10D 64/256 (2025.01); H10D 86/201 (2025.01);
Abstract

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a silicon-on-insulator substrate including a semiconductor layer, a semiconductor substrate, and a dielectric layer between the semiconductor layer and the semiconductor substrate. The semiconductor substrate includes first and second doped regions, the first doped region has a first conductivity type, and the second doped region has a second conductivity type different from the first conductivity type. The structure further comprises first and second source/drain regions in the semiconductor layer, and a gate structure laterally between the first source/drain region and the second source/drain region. The first source/drain region overlaps with the first doped region, and the second source/drain region overlaps with the second doped region.


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