Semiconductor structure including bit lines and fabrication method thereof

Abstract

The method includes: providing a substrate; forming bit lines arranged at intervals along a first direction on the substrate, a width of a top of each bit line being greater than a width of a bottom of each bit line; forming an initial isolation spacer covering each bit line, the initial isolation spacer including a first initial isolation layer, a second isolation layer and a third initial isolation layer stacked, where the first initial isolation layer covers the bit lines, the second isolation layer is positioned between the first initial isolation layer and the third initial isolation layer, and a top surface of the second isolation layer is lower than a top surface of the first initial isolation layer; and removing the initial isolation spacer positioned on the substrate between adjacent bit lines, where a retained part of the initial isolation spacer constitutes an isolation spacer.