The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Feb. 01, 2021
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Thomas Kuenemund, Munich, DE;

Markus Gruetzner, Munich, DE;

Peter Egger, Baldham, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/336 (2006.01); H01L 23/00 (2006.01); H03K 19/003 (2006.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H01L 23/573 (2013.01); H03K 19/00315 (2013.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01);
Abstract

Various embodiments describe an integrated circuit. The integrated circuit includes at least seven planar field effect transistors provided in a common substrate next to one another with a maximum feature size in accordance with a technology node of a maximum of 65 nm. Each field effect transistor of the at least seven planar field effect transistors includes a first source/drain diffusion region, a second source/drain diffusion region, a channel region between the drain diffusion region and the source diffusion region, and a gate terminal. Each field effect transistor of the at least seven planar field effect transistors includes at least one common source/drain diffusion region with another field effect transistor of the at least seven planar field effect transistors. The common source/drain diffusion regions are free of vertical terminal contact material.


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