The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

May. 26, 2022
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Shiqian Shao, Fremont, CA (US);

Tuan Pham, San Jose, CA (US);

Fumiaki Toyama, Cupertino, CA (US);

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/04 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
G11C 16/0483 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

A non-volatile memory apparatus comprises a stack of integrated memory assemblies. Each integrated memory assembly includes a memory die bonded to a control die and a set of power pads connected to metal lines in the respective memory die and control die. The memory dies comprise a non-volatile memory structure and a top metal layer for transmitting power signals above the memory structure. The control dies comprise a substrate, a control circuit positioned on the substrate for performing memory operations on a corresponding memory structure and a set of metals layers above the control circuit. The substrate comprises a set of conductive vias through the substrate that connect at one end to the top metal layer of the memory die of an adjacent integrated memory assembly and connect at a second end to the set of metals layers above the control circuit for routing signals between integrated memory assemblies.


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