The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2025
Filed:
Mar. 25, 2022
Synopsys, Inc., Mountain View, CA (US);
Subramanyam Sripada, Portland, OR (US);
Song Chen, San Jose, CA (US);
Synopsys, Inc., Sunnyvale, CA (US);
Abstract
A system performs timing analysis of three-dimensional integrated circuits (3DICs). The circuit design is targeted for implementation on a stacked die that has a plurality of dies. The circuit design includes portions of the circuit design, each portion of the targeted for a different die. The system selects a net that crosses die boundaries and determines a plurality of sets of timing values of the net. The system determines a worst case slack value for the net based on the sets of timing values. The system determines a timing adjustment value for the net based on aggregate timing values determined from the sets of timing values. The system adjusts the worst case slack value for a net based on the timing adjustment value for each load pin of the net. The adjustment of the worst case slack reduces pessimism of the worst case slack value.