The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Nov. 29, 2021
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Barton L. Quayle, San Jose, CA (US);

Chi Ming Yeung, Dublin, CA (US);

Choshu Ito, San Mateo, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 111/02 (2020.01); G06F 111/20 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 2111/02 (2020.01); G06F 2111/20 (2020.01);
Abstract

Embodiments include herein are directed towards a system and method for circuit emulation. Embodiments may include one or more domains of system components, each respective domain comprising one or more processors of the emulation system. Each respective processor may be configured to execute one or more processing jobs according to an instruction set executed by the respective processor. Embodiments may include a system manager module configured to control an emulation associated with a first domain and identify at least one unused pin associated with the first domain. The system manager module may be configured to allow access to the at least one unused pin for a second domain during the emulation of the first design.


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