The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2025

Filed:

Dec. 23, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Anant Nori, Bangalore, IN;

Rahul Bera, Zürich, CH;

Shankar Balachandran, Bangalore, IN;

Joydeep Rakshit, Bengaluru, IN;

Om Ji Omer, Bangalore, IN;

Sreenivas Subramoney, Bangalore, IN;

Avishaii Abuhatzera, Amir, IL;

Belliappa Kuttanna, Austin, TX (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0811 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06N 3/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 9/3012 (2013.01); G06F 9/3851 (2013.01); G06F 9/3888 (2023.08); G06F 9/4881 (2013.01); G06N 3/02 (2013.01);
Abstract

Apparatus and method for leveraging simultaneous multithreading for bulk compute operations. For example, one embodiment of a processor comprises: a plurality of cores including a first core to simultaneously process instructions of a plurality of threads; a cache hierarchy coupled to the first core and the memory, the cache hierarchy comprising a Level 1 (L1) cache, a Level 2 (L2) cache, and a Level 3 (L3) cache; and a plurality of compute units coupled to the first core including a first compute unit associated with the L1 cache, a second compute unit associated with the L2 cache, and a third compute unit associated with the L3 cache, wherein the first core is to offload instructions for execution by the compute units, the first core to offload instructions from a first thread to the first compute unit, instructions from a second thread to the second compute unit, and instructions from a third thread to the third compute unit.


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