The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Jul. 13, 2022
Applicant:

Leap Semiconductor Corp., Taoyuan, TW;

Inventors:

Wei-Fan Chen, Taichung, TW;

Kuo-Chi Tsai, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/03 (2025.01); H10D 12/01 (2025.01); H10D 30/65 (2025.01); H10D 62/832 (2025.01);
U.S. Cl.
CPC ...
H10D 84/035 (2025.01); H10D 12/031 (2025.01); H10D 30/658 (2025.01); H10D 62/8325 (2025.01);
Abstract

A method of manufacturing a silicon carbide semiconductor power device is provided. In the method, the power device in high voltage (HV) region and CMOS device in the low voltage (LV) region are formed together, so the cost and time can be saved efficiently. First, a first drift layer is formed on a substrate, and then a shielding region is formed in the first drift layer. The shielding region includes a continuous region in the LV region. Then, a second drift layer is formed on the first drift layer. A pick-up region is formed in the second drift layer, wherein the pick-up region connects to the continuous region of the shielding region, and then NMOS and PMOS in the LV region and the power device in HV region are formed simultaneously. NMOS and PMOS are surrounded by the pick-up region and the continuous region, thereby minimizing body effect.


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