The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Apr. 20, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Bo-Feng Young, Taipei, TW;

Sai-Hooi Yeong, Zhubei, TW;

Chi On Chui, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/3065 (2006.01); H01L 21/762 (2006.01); H10D 30/01 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H01L 21/02532 (2013.01); H01L 21/26513 (2013.01); H01L 21/3065 (2013.01); H01L 21/76224 (2013.01); H10D 30/024 (2025.01); H10D 62/151 (2025.01); H10D 62/292 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0172 (2025.01); H10D 84/0188 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01);
Abstract

An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.


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