The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2025
Filed:
Jan. 25, 2022
Applicant:
Applied Materials, Inc., Santa Clara, CA (US);
Inventors:
Ashish Pal, San Ramon, CA (US);
El Mehdi Bazizi, San Jose, CA (US);
Benjamin Colombeau, San Jose, CA (US);
Myungsun Kim, Pleasanton, CA (US);
Assignee:
Applied Materials, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 30/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 30/501 (2025.01); H10D 30/502 (2025.01); H10D 30/507 (2025.01); H10D 62/123 (2025.01); Y10S 977/938 (2013.01);
Abstract
Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.