The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Nov. 16, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Seongkeun Cho, Suwon-si, KR;

Jae Seong Park, Seoul, KR;

Youngseok Kim, Seoul, KR;

Young Sin Kim, Hwaseong-si, KR;

Daeyoung Moon, Seoul, KR;

Keum Joo Lee, Hwaseong-si, KR;

Sung-Wook Jung, Seoul, KR;

Sungduk Hong, Yongin-si, KR;

Suhwan Hwang, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H10B 12/315 (2023.02); G11C 5/063 (2013.01); H10B 12/50 (2023.02);
Abstract

A semiconductor memory device includes a substrate including a cell area and a peripheral area defined by a periphery of the cell area, the cell area including a dummy cell area and a normal cell area, and an active area defined by a cell element isolation film. The device includes a cell area separation film defining the cell area in the substrate, the dummy cell area defining a boundary with the cell area separation film between the normal cell area and the cell area separation film. The device includes a normal bit-line on the normal cell area and extending in a first direction, a dummy bit-line group on the dummy cell area, the dummy bit-line group including a plurality of dummy bit-lines extending in the first direction, and a plurality of storage contacts connected to the active area and located along a second direction perpendicular to the first direction.


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