The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Jun. 21, 2024
Applicant:

Celestial Ai Inc., Santa Clara, CA (US);

Inventors:

Matteo Staffaroni, San Ramon, CA (US);

Kevin Park, Santa Clara, CA (US);

Saurabh Vats, Palo Alto, CA (US);

Subal Sahni, La Jolla, CA (US);

Ismail Hakki Ozguc, Santa Clara, CA (US);

Assignee:

Celestial AI Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); G02B 6/12 (2006.01); G02B 6/122 (2006.01); G02B 6/13 (2006.01); G02B 6/42 (2006.01); H01L 25/16 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); G02B 6/12004 (2013.01); G02B 6/1225 (2013.01); G02B 6/13 (2013.01); G02B 6/428 (2013.01); H01L 25/167 (2013.01); G02B 2006/1213 (2013.01); G02B 2006/12142 (2013.01); H01L 2223/58 (2013.01);
Abstract

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.


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