The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Mar. 06, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Chun S. Yeung, San Jose, CA (US);

Deping He, Boise, ID (US);

Jonathan S. Parry, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2006.01); G11C 7/04 (2006.01); G11C 29/12 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 7/04 (2013.01); G11C 29/1201 (2013.01); G11C 29/4401 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01);
Abstract

Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.


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