Semiconductor memory with adjustment circuit and method for controlling a semiconductor memory

Abstract

A semiconductor memory is provided to include an adjustment circuit. The adjustment circuit sets a second period longer than a first period and adjusts time at which the last read data is output. When a chip selection signal is set to be asserted, the semiconductor memory device performs a read operation on data according to an external clock signal. The first period begins at a rising edge or a falling edge of the external clock signal and ends when the output of the last read data begins. The second period begins when the chip selection signal goes from asserted to negated and ends when the output of the last read data is complete. The external clock signal is used to read the last read data during the read operation.