The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2025
Filed:
Oct. 31, 2022
Cadence Design Systems, Inc., San Jose, CA (US);
Kwangsoo Han, Austin, TX (US);
Zhuo Li, Austin, TX (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Aspects of the present disclosure address systems and methods for applying logic sharing transformations to integrated circuit designs. Consistent with some embodiments, a cube-literal matrix is generated for an integrated circuit design. The cube-literal matrix comprises a non-unique matrix representation of functional logic in the integrated circuit design. A candidate cube is extracted from the cube-literal matrix to evaluate for application of a logic sharing transformation. The candidate cube comprises a sub-matrix of the cube-literal matrix corresponding to two or more common inputs of two or more logical operators. Based on determining that application of the logic sharing transformation to the candidate cube results in a reduction to a literal count in the integrated circuit design, the cube-literal matrix is updated to reflect the application of the logic sharing transformation to the candidate cube and the integrated circuit design is updated based on the updated cube-literal matrix.