The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2025
Filed:
Mar. 30, 2022
Phytium Technology Co., Ltd., Tianjin, CN;
Xiaokun Luan, Tianjin, CN;
Jianfeng Jiang, Tianjin, CN;
Wei Huang, Tianjin, CN;
Shaoxian Bian, Tianjin, CN;
Yongfeng Sun, Tianjin, CN;
Yu Deng, Tianjin, CN;
Zhanzhi Chen, Tianjin, CN;
Wenjiang Jin, Tianjin, CN;
Cuina Wang, Tianjin, CN;
Tao Tang, Tianjin, CN;
Phytium Technology Co., Ltd., Tianjin, CN;
Abstract
A clock design method for two or more physical partition structures based on a same system clock. The method includes determining a distance of each circuit logic from the system clock; based on the distance between each circuit logic and the system clock, obtaining a plurality of clock nodes from the system clock to cause a delay of each clock node compared to the system clock to change with the distance from each circuit logic and the system clock, the greater the distance, the greater the delay; connecting each circuit logic to a corresponding clock node based on size of each circuit logic and the distance; and converging timing of each circuit logic by adjusting the delay of each clock node compared to the system clock.