The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Jun. 03, 2022
Applicant:

Sifive, Inc., San Mateo, CA (US);

Inventors:

Ernest L. Edgar, Colorado Springs, CO (US);

Yann Loisel, La Ciotat, FR;

Assignee:

SiFive, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/4401 (2018.01); G06F 11/362 (2025.01); G06F 12/02 (2006.01); G06F 12/1027 (2016.01); G06F 12/14 (2006.01); G06F 21/53 (2013.01); G06F 21/57 (2013.01); G06F 21/74 (2013.01);
U.S. Cl.
CPC ...
G06F 9/3861 (2013.01); G06F 9/4403 (2013.01);
Abstract

Systems and methods are disclosed for debug in a system on a chip with a securely partitioned memory space. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions, including a data store configured to store a first world identifier; an outer memory system configured to store instructions and data; a data store configured to store a debug world list that specifies which world identifiers supported by the integrated circuit are authorized for debugging; and a debug enable circuitry configured to generate a debug enable signal based on the first world identifier and the debug world list, wherein the processor core is configured to jump to debug handler instructions in response to a debug exception or ignore the debug exception depending on the debug enable signal.


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