The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Apr. 13, 2023
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Po-Kai Hsu, Tainan, TW;

Chung-Yi Chiu, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10N 70/00 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H10N 70/8833 (2023.02); H10B 63/30 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/841 (2023.02);
Abstract

An RRAM structure includes a substrate. A transistor is disposed on the substrate, wherein the transistor includes a gate structure, a source and a drain. An interlayer dielectric layer covers the transistor. A drain contact plug is disposed within the interlayer dielectric layer and contacts the drain, and wherein an end of the drain contact plug protrudes from the interlayer dielectric layer. A metal interlayer dielectric layer is disposed on and contacts the interlayer dielectric layer. A resistive random access memory (RRAM) is disposed on the drain and within a first trench in the metal interlayer dielectric layer, wherein the RRAM includes a bottom electrode, a metal oxide layer and a top electrode, the drain contact plug contacts the bottom electrode, the bottom electrode contacts the metal oxide layer and the top electrode contacts the metal oxide layer. A metal layer is disposed within the first trench.


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