The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Apr. 17, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Yu-Lien Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/27 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 64/518 (2025.01); H10D 30/024 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01);
Abstract

Embodiments of the present disclosure relates to a semiconductor device structure, including a first gate dielectric layer having a top surface and a corner surface, wherein a highest point of the top surface of the first gate dielectric layer is at a first elevation. The semiconductor device structure includes a first gate electrode layer having a top surface, wherein a highest point of the top surface of the first gate electrode layer is at a second elevation higher than the first elevation. The semiconductor device structure includes a first dielectric cap layer in contact with the top surface and the corner surface of the first gate dielectric layer. The first dielectric cap layer is also in contact with the top surface of the first gate electrode layer. The semiconductor device structure includes a first gate spacer in contact with the first dielectric cap layer and the first gate dielectric layer.


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