The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Apr. 15, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ming-Lung Cheng, Kaohsiung, TW;

Huang-Hsuan Lin, Hsinchu, TW;

Chih-Chieh Yeh, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/02 (2006.01); H01L 21/28 (2025.01); H01L 21/3213 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H10D 64/01 (2025.01); H01L 21/0259 (2013.01); H01L 21/28088 (2013.01); H01L 21/32133 (2013.01); H10D 30/031 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/679 (2025.01);
Abstract

A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a work function layer surrounding the nanostructures. The method also includes forming spacers over opposite sides of the work function layer. The method also includes forming a first metal layer over the work function layer and sidewalls of the spacers. The method also includes forming a second metal layer surrounded by the first metal layer. The method also includes etching the first metal layer over opposite sides of the second metal layer. The method also includes forming a cap layer over a top surface and a sidewall of the second metal layer.


Find Patent Forward Citations

Loading…