Semiconductor device having nanosheet transistor and methods of fabrication thereof

Abstract

A semiconductor device structure is provided. The device includes a plurality of semiconductor layers vertically stacked, and a gate electrode layer comprising an upper portion disposed between two adjacent gate spacers, the upper portion having a first diameter. The gate electrode layer also includes a lower portion disposed below the upper portion including a first part surrounding each semiconductor layer of the plurality of semiconductor layers and a second part adjacent the first part, the second part comprising a first section having a second diameter that is less than the first diameter, a second section below the first section, the second section having a third diameter different than the second diameter, and a third section below the second section, wherein the third section has a fourth diameter different than the second diameter and the third diameter, wherein the first and second parts are formed as an integral.