The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Apr. 26, 2023
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Po-Hsien Yeh, Taichung, TW;

Jih-Wen Chou, Hsinchu, TW;

Hwi-Huang Chen, Hsinchu, TW;

Hsin-Hong Chen, Hsinchu, TW;

Yu-Jen Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/223 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H01L 21/02 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H10D 30/015 (2025.01); H01L 21/2233 (2013.01); H01L 21/2236 (2013.01); H10D 30/475 (2025.01); H01L 21/022 (2013.01); H01L 23/291 (2013.01); H01L 23/3171 (2013.01); H01L 23/3192 (2013.01);
Abstract

A GaN device with Npre-treatment is provided in the present invention, including a GaN substrate, an AlGaN layer covering the GaN substrate, a p-GaN gate on the AlGaN layer, a TiN electrode on the p-GaN gate, a first dielectric layer on the AlGaN layer surrounding the p-GaN gate, wherein a horizontal spacing is between the first dielectric layer and the p-GaN gate, and an interface between the AlGaN layer and the GaN substrate not covered by the first dielectric layer is subject to Npre-treatment, and a second dielectric layer covering on and directly contacting the exposed first dielectric layer, AlGaN layer, p-GaN gate and TiN electrode.


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