The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Nov. 29, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yan-Jhih Huang, Hsinchu, TW;

Chun-Yuan Hsu, Hsinchu, TW;

Chien-Chung Chen, Hsinchu, TW;

Yung-Hsieh Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 1/68 (2025.01); H01L 23/522 (2006.01); H10D 1/00 (2025.01); H10B 41/30 (2023.01); H10D 64/01 (2025.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H10D 1/692 (2025.01); H01L 23/5223 (2013.01); H10D 1/042 (2025.01); H10D 1/714 (2025.01); H01L 23/5222 (2013.01); H01L 2924/00 (2013.01); H01L 2924/0002 (2013.01); H10B 41/30 (2023.02); H10D 1/68 (2025.01); H10D 64/035 (2025.01); H10D 89/10 (2025.01);
Abstract

A method of making a semiconductor device includes forming a circuit layer over a substrate. The method further includes depositing an insulator over the substrate. The method further includes patterning the insulator to define a test line trench, a first trench, and a second trench, wherein the first trench is on a portion of the substrate exposed by the circuit layer. The method further includes filling the test line trench to define a test line electrically connected to the circuit layer. The method further includes filling the first trench and the second trench to define a capacitor.


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