The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Apr. 26, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Meng-Han Lin, Hsinchu, TW;

Feng-Cheng Yang, Hsinchu County, TW;

Sheng-Chen Wang, Hsinchu, TW;

Han-Jong Chia, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/30 (2023.01); H10B 51/20 (2023.01); H10B 51/40 (2023.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/80 (2025.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); H10B 51/20 (2023.02); H10B 51/40 (2023.02); H10D 30/6735 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/80 (2025.01);
Abstract

A memory device, a semiconductor device and a manufacturing method of the memory device are provided. The memory device includes first, second and third stacking structures, first and second channel structures, a gate dielectric layer, a switching layer, and first and second gate structures. The first, second and third stacking structures are laterally spaced apart from one another, and respectively comprise a conductive layer, an isolation layer and a channel layer. The third stacking structure is located between the first and second stacking structures. The first channel structure extends between the channel layers in the first and third stacking structures. The second channel structure extends between the channel layers in the second and third stacking structures. The gate dielectric layer and the first gate structure wrap around the first channel structure. The switching layer and the second gate structure wrap around the second channel structure.


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