The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

May. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hung-Li Chiang, Taipei, TW;

Jer-Fu Wang, Taipei, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Meng-Fan Chang, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); G11C 5/06 (2006.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 64/00 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); G11C 5/063 (2013.01); H10B 51/10 (2023.02); H10D 30/024 (2025.01); H10D 30/0415 (2025.01); H10D 30/6211 (2025.01); H10D 30/701 (2025.01); H10D 64/033 (2025.01); H10D 64/689 (2025.01); H10B 12/01 (2023.02);
Abstract

A memory device including a plurality of memory cells, at least one of the plurality of memory cells includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first drain/source path and a first gate structure electrically coupled to a write word line. The second transistor includes a second drain/source path and a second gate structure electrically coupled to the first drain/source path of the first transistor. The third transistor includes a third drain/source path electrically coupled to the second drain/source path of the second transistor and a third gate structure electrically coupled to a read word line. Where, the first transistor, and/or the second transistor, and/or the third transistor is a ferroelectric field effect transistor or a negative capacitance field effect transistor.


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