The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Feb. 08, 2022
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Xiaoling Wang, Hefei, CN;

Hai-Han Hung, Hefei, CN;

Min-Hui Chang, Hefei, CN;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H01L 21/762 (2006.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10B 12/31 (2023.02); H01L 21/762 (2013.01); H10B 12/482 (2023.02); H10B 12/488 (2023.02); H10D 62/115 (2025.01);
Abstract

A preparation method for a semiconductor structure includes the following operations. A bit line structure, active pillars, and a word line structure are formed in turn on a substrate. Bottom ends of the active pillars are connected to the bit line structure, and the active pillars are connected with the word line structure. A pillar-shaped conductive structure is formed on the active pillars, and a cup-shaped conductive structure is formed on the pillar-shaped conductive structure. There is an electrode gap between the pillar-shaped conductive structure and the cup-shaped conductive structure, and the pillar-shaped conductive structure and the cup-shaped conductive structure form a lower electrode. A dielectric layer is formed on a surface of the lower electrode. An upper electrode is formed on a surface of the dielectric layer. The upper electrode fills the electrode gap.


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