The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Aug. 30, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Travis M. Jensen, Boise, ID (US);

Walter L. Moden, Boise, ID (US);

Stephen F. Moxham, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H01L 21/48 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H05K 3/00 (2006.01); H05K 3/40 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/116 (2013.01); H01L 21/4846 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H05K 3/0014 (2013.01); H05K 3/0047 (2013.01); H05K 3/4038 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H05K 2201/09563 (2013.01); H05K 2201/09636 (2013.01);
Abstract

Substrates with continuous slot vias are disclosed herein. In one embodiment, a substrate comprises a first design layer, a second design layer, and an intermediary layer between the first and second design layers. The substrate further includes first and second signaling vias extending vertically through the intermediary layer between the first and second design layers. The first and second signaling vias route first and second data signals, respectively, between the first and second design layers. The substrate further includes a slot via that is positioned between the first and second signaling vias within the intermediary layer and extends laterally within the intermediary layer along a path that passes between the first signaling via and the second signaling via. The slot via can have a continuous shape such that the slot via shields the first and second data signals on the first and second signaling vias from crosstalk with one another.


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