Back-end-of-line cmos inverter having reduced size and reduced short-channel effects and methods of forming the same

Abstract

An embodiment inverter circuit may include a gate electrode formed over an interlayer dielectric layer, a gate dielectric layer formed over the gate electrode, a first-conductivity-type semiconductor layer formed over the gate dielectric layer, a second-conductivity-type semiconductor layer formed over the gate dielectric layer and laterally displaced from the first-conductivity-type semiconductor layer, a first source electrode formed in contact with the first-conductivity-type semiconductor layer, a second source electrode formed in contact with the second-conductivity-type semiconductor layer, and a shared drain electrode formed in contact with the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. At least one of the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer may include a metal-oxide semiconductor and/or a multi-layer structure formed in a back-end-of-line (BEOL) process that may be incorporated with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices.